| Package | 32-lead LFCSP |
| DAC type | Current Out |
| Interface | Parallel CMOS |
AD9705BCPZRL7 представляет собой 10-разрядный токовый ЦАП серии TxDAC с максимальной скоростью обновления 175 MSPS, оптимизированный для работы от одиночного питания 1.7 V…3.6 V.
Он обеспечивает полношкальный выходной ток 1 mA…5 mA при питании 3.3 V и до 2.5 mA при питании 1.8 V.
Встроенный опорный источник 1.0 V и регулируемый общий режим выхода 0 V…1.2 V упрощают согласование с последующим трактом.
Устройство реализовано в компактном корпусе 32-lead LFCSP с токовым дифференциальным выходом и параллельным CMOS-интерфейсом данных.
| Package | 32-lead LFCSP |
| DAC type | Current Out |
| Interface | Parallel CMOS |
| Resolution | 10 bit |
| Part number | AD9705BCPZRL7 |
| Manufacturer | Analog Devices, Inc. |
| Offset error | -0.03% of FSR to +0.03% of FSR |
| Glitch impulse | 5 pV-s |
| AVDD (1.8 V mode) | 1.7 V to 1.8 V |
| AVDD (3.3 V mode) | 3.3 V to 3.6 V |
| DVDD (1.8 V mode) | 1.7 V to 1.8 V |
| DVDD (3.3 V mode) | 3.3 V to 3.6 V |
| Data input format | 2s Comp., Straight Binary |
| Input capacitance | 5 pF |
| Output resistance | 200 MΩ |
| Number of channels | 1 |
| Output capacitance | 5 pF |
| CLKVDD (1.8 V mode) | 1.7 V to 1.8 V |
| CLKVDD (3.3 V mode) | 3.3 V to 3.6 V |
| Supply voltage range | 1.7 V to 3.6 V |
| Reference voltage drift | ±25 ppm/°C |
| Thermal resistance θJA | 32.5 °C/W |
| Reference output current | 100 nA |
| On-chip reference voltage | 0.98 V to 1.08 V (typ 1.025 V) |
| Storage temperature range | -65 °C to +150 °C |
| Clock differential voltage | 0.5 V to 1.5 V |
| Maximum output update rate | 175 MSPS |
| Operating temperature range | -40 °C to +85 °C |
| Output settling time to 0.1% | 11 ns |
| Common-mode output range OTCM | 0 V to 1.2 V |
| Logic 0 input voltage (1.8 V) | 0 V to 0.5 V |
| Logic 0 input voltage (3.3 V) | 0 V to 0.9 V |
| Logic 1 input voltage (1.8 V) | 1.2 V to 1.8 V |
| Logic 1 input voltage (3.3 V) | 2.1 V to 3 V |
| Output fall time (10% to 90%) | 2.5 ns |
| Output rise time (10% to 90%) | 2.5 ns |
| Clock power-down IDVDD (1.8 V) | 0.22 mA to 0.28 mA |
| Clock power-down IDVDD (3.3 V) | 0.6 mA to 1 mA |
| Latch pulse width tLPW (1.8 V) | 4 ns |
| Latch pulse width tLPW (3.3 V) | 2.8 ns |
| Output compliance range (3.3 V) | -0.8 V to +0.8 V |
| Sleep mode supply current IAVDD | 0.3 mA to 0.4 mA |
| Clock power-down ICLKVDD (1.8 V) | 9.5 µA to 16 µA |
| Clock power-down ICLKVDD (3.3 V) | 42.5 µA to 64 µA |
| Output propagation delay (1.8 V) | 5.6 ns |
| Output propagation delay (3.3 V) | 4 ns |
| Reference input compliance range | 0.1 V to 1.25 V |
| Clock common-mode voltage (1.8 V) | 0.4 V to 1.3 V |
| Clock common-mode voltage (3.3 V) | 0.75 V to 2.25 V |
| Clock input voltage range (1.8 V) | 0 V to 1.8 V |
| Clock input voltage range (3.3 V) | 0 V to 3 V |
| Analog supply current IAVDD (3.3 V) | 5.1 mA to 6.7 mA |
| Clock supply current ICLKVDD (3.3 V) | 4.1 mA to 4.7 mA |
| Digital supply current IDVDD (3.3 V) | 5.0 mA to 6.6 mA |
| Absolute maximum junction temperature | 150 °C |
| Maximum output update rate (1.8 V mode) | 125 MSPS |
| Full-scale output current (AVDD = 1.8 V) | 1 mA to 2.5 mA |
| Full-scale output current (AVDD = 3.3 V) | 1 mA to 5 mA |
| Gain drift (with internal reference, 3.3 V) | ±40 ppm of FSR/°C |
| Gain error (with internal reference, 3.3 V) | -2.7% of FSR to +2.7% of FSR |
| Output compliance range (1.8 V, OTCM = AGND) | -0.8 V to +0.8 V |
| Power-down mode supply current IAVDD (3.3 V) | 5 µA to 7 µA |
| Input hold time tH (1.8 V, -40 °C to +85 °C) | 0.1 ns |
| Input hold time tH (3.3 V, -40 °C to +85 °C) | 0.6 ns |
| Input setup time tS (1.8 V, -40 °C to +85 °C) | 2.4 ns |
| Input setup time tS (3.3 V, -40 °C to +85 °C) | 1.6 ns |
| Power dissipation (1.8 V, 80 MSPS, IOUTFS = 1 mA) | 11.1 mW to 13.2 mW |
| Analog supply current IAVDD (1.8 V, IOUTFS = 1 mA) | 3.8 mA to 4.8 mA |
| Power dissipation (3.3 V, 175 MSPS, IOUTFS = 2 mA) | 46.9 mW to 57 mW |
| Clock supply current ICLKVDD (1.8 V, IOUTFS = 1 mA) | 1.3 mA to 1.5 mA |
| Digital supply current IDVDD (1.8 V, IOUTFS = 1 mA) | 1.1 mA to 1.5 mA |
| Integral nonlinearity INL (3.3 V, precalibration, typ) | ±0.10 LSB |
| Power-down mode supply current IAVDD (3.3 V, alt spec) | 0.7 µA to 7.5 µA |
| Differential nonlinearity DNL (3.3 V, precalibration, typ) | ±0.09 LSB |
| Noise spectral density (3.3 V, fCLOCK = 175 MSPS, fOUT = 6.0 MHz, IOUTFS = 2 mA) | -144 dBc/Hz |
| Spurious-free dynamic range to Nyquist (3.3 V, fCLOCK = 175 MSPS, fOUT = 20.1 MHz) | 75 dBc |
Предлагаем ЦАП Analog Devices AD9705BCPZRL7, 10-разрядный, 175 MSPS TxDAC на выгодных условиях с полной технической поддержкой. Проверим наличие, поможем подобрать аналог.
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